Intel Shows Off Work on Next-Gen Glass Core Substrates, Plans Deployment Later in Decade

Although Intel’s yearly Innovation arena doesn’t footwear disconnected until tomorrow, nan institution is already publishing immoderate announcements up of nan show – and it’s not nan trivial stuff, either. This greeting nan institution is showing disconnected their first activity connected processing a solid halfway substrate and associated packaging process for their chips. As a consequence of their advancement pinch investigation and improvement connected nan solid cores, Intel is now readying connected introducing solid halfway substrates to its products successful nan 2nd half of this decade, allowing them to package chips successful much complex, and yet higher-performing configurations.

There’s a batch to unpack from Intel’s comparatively short announcement, but astatine a precocious level, solid halfway substrates person been nether investigation for complete a decade arsenic a replacement for integrated substrates, which are wide utilized successful current-generation processors. Essentially nan mean that emblematic silicon dies beryllium on, substrates play an important portion successful spot packaging. First and foremost, they supply nan structural stableness for a spot (silicon dies are rather vulnerable and flimsy), and they are besides nan intends done which signals from silicon dies are carried, either to different on-package dies (i.e. chiplets), aliases to nan ample number of comparatively sizable pins/pads connected nan backmost broadside of a chip. And, arsenic spot sizes person accrued complete nan years – and nan number of pins/signals required by high-end chips has, arsenic good – truthful has nan request for newer and amended materials to usage arsenic a substrate, which is what’s been driving Intel’s latest accomplishment.

Ultimately, what Intel is aiming to do pinch solid halfway substrates is to amended upon what tin beryllium done pinch existing integrated substrates, allowing for larger chips pinch much signals to beryllium routed done nan substrate much cleanly. And while this will perchance person benefits for each chips complete a agelong capable time, nan contiguous attraction is connected high-end, multi-chiplet processors, wherever solid halfway substrates will connection amended mechanical stability, amended awesome integrity, and nan expertise to much easy way a larger number of signals done a non-silicon medium. In short, Intel considers it 1 of nan keys to making high-performance processors successful nan adjacent decade.

Substrates: A Quick Recap

The request for substrates goes backmost to immoderate of nan earliest days for large-scale integrated chips, wherever spot designs reached thousands and tens of thousands of transistors. These mini transistors needed to beryllium wired to overmuch larger pins successful bid to beryllium installed successful systems by comparatively monolithic quality hands, starring up to nan first spot packages, specified arsenic dual in-line packages. These utilized a framework – typically a lead frame – to clasp nan existent silicon die, pinch nan framework (or alternatively, ligament bonds) providing nan awesome paths betwixt nan dice and outer pins.

Intel 4004 Delidded (Image Courtesy Science Museum Group Collection Online - CC BY-SA 4.0)

Since nan 70s, location person been respective evolutions successful substrate designed. Metal frames gave measurement to classical ceramic spot successful nan 90s, and past integrated packaging astir nan move of nan millennium. Each loop of substrate had amended properties than nan last, supra each else, making it easier to way a larger number of awesome and powerfulness pins to progressively analyzable dies.

While you’ll still find lead framework and ceramic chips present and there, integrated substrates person been nan breadstuff and food of nan manufacture for nan past mates of decades. The integrated material, fundamentally made of PCB-like worldly layered pinch woven solid laminates, allows for a reasonably ample number of signals to beryllium routed done a chip, including basal chiplet designs specified arsenic Intel’s mobile processors (with PCH abstracted PCH and CPU dies) arsenic good arsenic AMD’s chiplet-based Zen processors.

But integrated substrates person already been a limiting facet for immoderate clip now, particularly successful high-end chips. Which is why complete nan past decade we’ve seen nan emergence of ultra-high-density interconnect interfaces specified arsenic silicon interposers (chip connected wafer connected substrate), and their derivatives for illustration Intel’s ain EMIB. These person allowed companies to span together nan captious paths of their chips pinch accelerated and dense pieces of silicon, but astatine reasonably precocious costs, and without wholly resolving nan drawbacks of integrated substrates. As a result, Intel has besides been searching for a existent replacement for integrated substrates, 1 that will play nicely pinch ample chips, and while not replacing nan request for CoWoS/EMIB astatine nan highest level, would connection amended awesome capacity and denser routing than integrated substrates today.

Glass Core Substrates: Finer, Yet Stronger

This brings america to nan taxable of today’s announcement from Intel, solid halfway substrates. The institution has been moving connected replacing integrated substrates pinch solid for complete a decade now, and they’ve yet reached nan constituent of advancement wherever they’re fresh to show it disconnected to nan world while readying for its usage successful early products.

At a precocious level, a solid halfway substrate is conscionable that: replacing nan organic, PCB-like worldly of an integrated package pinch glass. To beryllium sure, this doesn’t mean replacing nan entire substrate pinch solid – truthful Intel is not going to beryllium mounting chips connected axenic pieces of solid – but rather, nan worldly astatine nan halfway of nan substrate would beryllium made of glass. Meanwhile, metallic redistribution layers (RDLs) would still beryllium coming connected some sides of a chip, providing nan existent pathways betwixt various pads and solder joints.

Glass Core Substrates In Panel Form

While harder to activity pinch than nan now well-established integrated substrate, Intel considers solid substrates to beryllium superior some successful mechanical and electrical properties, which successful move makes them desirable to usage successful early chips. Or, conversely, little undesirable than integrated substrates erstwhile building very ample chips.

Starting from nan mechanical broadside of matter, Intel reports that solid halfway substrates connection acold amended mechanical spot than integrated substrates. They’re capable to withstand higher temperatures amended than integrated substrates during packaging, resulting successful little warping and distortion. Glass is besides reportedly easier to get flatter arsenic well, which makes packaging and lithography easier. Finally, solid has a akin coefficient of thermal description arsenic silicon (unlike integrated substrates), meaning that what small warping that still occurs from power is accordant pinch nan dies above, arsenic opposed to having different parts of a spot expanding astatine different rates.

Most importantly, perhaps, is that each of those items taken together unfastened nan doorway to producing larger chips. With a much unchangeable substrate to equine nan dies on, it will beryllium imaginable to person larger dies and a larger number of dies each sharing a azygous substrate – and frankincense behaving arsenic a azygous chip.

Bridging nan spread betwixt mechanical and electrical, according to Intel, they’re besides capable to execute a overmuch tighter transportation connected nan through-glass vias (TGVs) that transportation signals done nan substrate itself, allowing for a overmuch larger number of vias overall. Intel is reporting that they’re capable to abstraction TGVs little than 100 microns (µm) apart, allowing for a 10-fold betterment successful TGV density. All of which yet allows for much elasticity successful routing signals done nan substrate core, and to immoderate grade makes it easier to way signals pinch less RDL layers.

Assembled Test Chip Substrates

All of this, successful turn, allows for not only larger chips, but for much dies to beryllium placed connected a same-sized chip. According to Intel, solid packaging would let them to spot 50% much dies connected a spot – aliases rather, nan dice analyzable area wrong a spot could beryllium 50% larger – allowing for much densely packed chips than what Intel tin do today.

Finally, connected nan electrical broadside of matters, solid halfway substrates, and much specifically nan TGVs, reportedly connection amended electrical capacity arsenic well. Owing to nan debased nonaccomplishment quality of nan dielectric utilized successful TGVs mixed pinch nan overmuch larger number of them, Intel says that solid halfway substrates will let for cleaner awesome routing and powerfulness delivery. In nan lawsuit of nan former, that intends being capable to do 448G signaling done copper, alternatively than having to usage optical interconnects. Meanwhile, lower-loss powerfulness transportation would amended wide spot ratio by that overmuch more, by reducing nan magnitude of power that is mislaid arsenic power earlier it moreover reaches nan processor dies.

Farther down nan statement still, solid halfway substrates should besides make co-packaged optics easier to execute for erstwhile you do want to usage optical. A solid substrate would let for optical interconnects to beryllium integrated correct into nan chip, alternatively than having to tack it connected successful different manners.

So if solid is truthful great, what’s nan catch? While Intel is understandably much excited to talk astir what’s bully astir solid halfway substrates and what they’ve recovered useful good frankincense far, 1 inescapable constituent will beryllium cost. Like immoderate caller technology, solid halfway substrates will beryllium much costly to nutrient and package pinch than tried and existent (and cheap) integrated substrates. And while Intel isn’t talking astir yields this acold out, it will beryllium difficult for solid to compete pinch organic, astatine slightest astatine first.

More broadly speaking, solid halfway substrates besides intends that Intel needs to bootstrap a complete ecosystem for nan material. They aren’t vertically integrated pinch integrated substrates today, and they won’t beryllium vertically integrated pinch glass, either. To that end, Intel is already moving pinch partners coming to create nan basal tooling and proviso capacity, to bring themselves to first commercialized production. But complete nan longer-term, Intel will request to fig retired really to make outsourced testing and assembly possible, particularly arsenic Intel plans to connection solid halfway substrates to IFS customers successful nan future.

Finally, it bears noting that while solid halfway substrates let for a tighter awesome transportation than integrated substrates, they are not a replacement for EMIB, Foveros, aliases different much precocious packing techniques based astir utilizing silicon mediums. A 75µm transportation for a TGV is still a acold outcry from nan 45µm transportation of EMIB, ne'er mind nan <10µm transportation planned for Foveros Direct. So each of those packaging technologies will stay complementary add-ons to solid halfway substrates, astatine champion replacing EMIB successful fringe cases of products that don’t request nan afloat density improvements of EMIB.

Glass In Action: Intel’s Fully Functional Test Chip

The last portion of today’s announcement from Intel is based astir nan manufacturing broadside of matters. As noted earlier, Intel has been moving connected solid halfway substrates for complete 10 years now, and much precocious has been embarking connected a three-and-a-half-year pathfinding task to bring solid halfway substrates to nan adjacent step. Backing those efforts, astatine this constituent nan institution has a afloat integrated R&D statement up and moving successful 1 of their Chandler, Arizona fabs (the aforesaid 1 that does EMIB). Altogether, Intel has spent complete a cardinal dollars connected solid halfway R&D frankincense far.

The first consequence of their R&D efforts, Intel has completed nan assembly of a group of trial vehicles – multi-chip packages built complete a solid substrate. The chips, which look akin to Intel’s ultra-low powerfulness mobile chips (Alder Lake-U 9W?), are reportedly afloat functional, giving Intel immoderate applicable results to study on. While we don’t person a ton of specifications connected nan chip, Intel has told america that it uses 3 layers of RDL, and nan TGVs person a transportation of 75µm.

Along pinch proving nan electrical properties of glass, nan mini trial spot is besides intended to beryllium immoderate of nan beingness properties, arsenic well. The solid halfway was made very heavy – connected nan bid of 1mm – successful bid to beryllium that TGVs would activity pinch specified a heavy core. For nan benignant of massive, high-end chips Intel is readying connected utilizing solid halfway packing for, those chips will require a very heavy halfway successful bid to deed their size goals, truthful Intel needed to beryllium that TGVs would (still) activity astatine specified lengths.

Intel Glass Core Substrates: Coming Later This Decade

Wrapping things up, today’s announcement serves arsenic a kick-off of sorts for Intel’s solid halfway substrate era. Following connected their decade of R&D activity and their pathfinding sprint, Intel now believes they are fresh to statesman readying for nan modulation to solid halfway substrates successful their products – albeit a modulation that is still respective years out.

If Intel’s merchandise improvement goes according to plan, nan institution intends to statesman shipping solid halfway products later this decade. The first products to get nan solid halfway substrate curen would beryllium their largest and astir profitable products, specified arsenic high-end HPC and AI chips. These are nan products astir strained by nan usage of integrated substrates coming owed to nan size limits those substrates impose, and those are nan limits intel believes would astir use from solid halfway packaging.

Longer-term, nan scheme is to waterfall down nan exertion from HPC chips into smaller and smaller chips, until nan exertion is disposable (and viable) for Intel’s rank and record user chips. The institution is very speedy to statement that solid and integrated substrates will co-exist for years to travel – and, for illustration past transitions, location will apt still beryllium chips utilizing integrated substrates good aft solid is introduced – but nan institution is besides optimistic that they’ll beryllium capable to bring nan costs of solid halfway substrates down to parity pinch integrated substrates, yet making it imaginable to reap nan benefits moreover successful lower-priced processors.

And Intel won’t beryllium keeping nan exertion to themselves, either. As portion of nan company’s broader inaugural to go a world people statement foundry, Intel will beryllium offering solid halfway substrates to IFS customers successful owed time. While it’s acold excessively early to conjecture erstwhile that would beryllium (even Intel products whitethorn beryllium 6 years out), being capable to connection solid packaging could springiness Intel a large limb up complete its competitors, particularly for producing high-end, highly-profitable chips.

Above each else, it needs to beryllium reiterated that there’s a awesome woody of activity Intel still needs to do successful bid to bring solid halfway substrates to nan market. But if nan institution is successful, past nan move to solid will usher successful nan benignant of awesome exertion modulation that only happens each 15 to 20 years.