Intel developing its own stacked cache tech to compete with AMD 3D V-Cache

Intel is moving connected its ain type of unchangeable cache that AMD pioneered pinch its 3D V-Cache technology, though it is still astatine slightest a mates of generations away.

Following Intel CEO Pat Gelsinger's Intel Innovation 2023 keynote, Gelsinger held a Q+A convention pinch members of nan property wherever he was asked if Intel would adopt nan aforesaid stackable cache exertion that AMD has been utilizing to make immoderate of nan best processors connected nan market. 

"When you reference V-Cache," Gelsinger said, arsenic reported by Tom's Hardware, "you're talking astir a very circumstantial exertion that TSMC does pinch immoderate of its customers arsenic well. Obviously, we're doing that otherwise successful our composition, right? And that peculiar type of exertion isn't thing that's portion of [the caller Intel Core Ultra processors], but successful our roadmap, you're seeing nan thought of 3D silicon wherever we'll person cache connected 1 die, and we'll person CPU compute connected nan stacked dice connected apical of it, and evidently utilizing [embedded multi-die interconnect bridges] that Foveros [chiplet packaging technology] we'll beryllium capable to constitute different capabilities."

Anyone who saw Gelsinger's keynote would person seen really Intel's upcoming processor roadmap will move heavy into nan multi-chiplet module (MCM) creation paradigm, wherever different processor components for illustration nan iGPU, cache, and Intel's caller nueral processing portion would beryllium discrete segments bonded together into a azygous portion alternatively than formed together each astatine once.

The MCM process allows for a batch much elasticity than nan much restrictive monolithic silicon fabrication that has traditionally been utilized previously, and would evidently unfastened up each sorts of caller possibilities for spot creation that weren't applicable utilizing a monolithic structure.

The astir evident of these is stacked cache, which greatly increases nan disposable cache representation excavation for nan processor that translates into overmuch faster processing of circumstantial CPU workloads.

AMD has already proven nan benefits of this expanded cache excavation erstwhile it launched nan AMD Ryzen 7 5800X3D spot successful 2022, followed by AMD Ryzen 7 7800X3D, AMD Ryzen 9 7900X3D, and AMD Ryzen 9 7950X3D earlier this year.

"We consciousness very bully that we person precocious capabilities for next-generation representation architectures, advantages for 3D stacking, for some small die, arsenic good arsenic for very large packages for AI and high-performance servers arsenic well," Gelsinger said. "So we person a afloat breadth of those technologies. We'll beryllium utilizing those for our products, arsenic good arsenic presenting it to nan [Intel] Foundry customers arsenic well."

Stackable cache is only nan opening for Intel's packaging tech

Intel's move into MCM processor creation utilizing its embedded multi-die interconnect span (EMIB) and Forveros spot packaging exertion is simply a awesome measurement guardant for nan chipmaker. 

The best Intel processors of nan past mates of years person relied heavy connected simply throwing earthy electrical powerfulness into its processors to summation performance, making its high-end Intel Core i9-12900K and Intel Core i9-13900K particularly powerfulness quiet processors.

This has allowed it to regain a batch of crushed mislaid to nan best AMD processors of nan past fewer years, but this isn't a workable agelong word solution, and moreover Nvidia is reportedly seeing nan contented of moving to an MCM design for its next-gen Nvidia Blackwell architecture.

And while nan thought of a early Intel processor, perchance arsenic soon arsenic Lunar Lake, featuring stacked cache is exciting, it should only beryllium nan opening of caller processor developments, not nan extremity of it.

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