AMD this greeting is releasing nan 4th and last personnel of its 4th procreation EPYC processor family, nan EPYC 8004 series. Previously disclosed nether nan codename Siena, nan EPYC 8004 bid is AMD’s low-cost sub-set of EPYC CPUs, aimed astatine nan telco, edge, and different value and efficiency-sensitive trading segments. Based connected nan aforesaid Zen4c cores arsenic Bergamo, Siena is fundamentally Bergamo-light, utilizing nan aforesaid hardware to connection server processors pinch betwixt 8 and 64 CPU cores.
First unveiled by AMD past summer astatine Financial Analyst Day 2022, Siena is AMD’s first dedicated introduction into nan telco, networking, and separator market. Compared to AMD’s general-purpose Genoa chips (EPYC 9004), Siena offers less CPU cores and little capacity overall, alternatively optimizing nan chips and level for little costs and amended power ratio for usage successful non-datacenter environments. More broadly speaking, Siena is functionally nan long-awaited low-end conception of nan 4th procreation EPYC stack.
Unlike nan motorboat of nan erstwhile 3 4th procreation EPYC segments – Genoa, Genoa-X, and Bergamo – nan motorboat of Siena is simply a lower-key affair. Besides nan reduced excitement that comes pinch nan motorboat of lower-end hardware, location is, strictly speaking, nary caller silicon progressive successful this launch. Siena is comprised of nan aforesaid 5nm Zen 4c halfway analyzable dice (CCD) chiplets arsenic Bergamo, which are paired pinch AMD’s 1 and only 6nm EPYC I/O Die (IOD). As a result, nan EPYC 8004 family isn’t truthful overmuch caller hardware arsenic it is simply a caller configuration of existing hardware – astir half of a Bergamo, springiness aliases take.
And that half Bergamo affinity isn’t conscionable astir CPU cores; it applies to nan remainder of nan level arsenic well. Underscoring nan entry-level quality of nan Siena platform, Siena ships pinch less DDR5 representation channels and less I/O lanes than its faster, fancier counterpart. Siena only offers 6 channels of DDR5 memory, down from 12 channels for different EPYC parts, and 96 lanes of PCIe Gen 5 alternatively of 128 lanes. As a result, while Siena is still a existent Zen 4 portion done and done (right connected down to AVX-512 support), it’s wide a noticeably lighter-weight level than nan different EPYC family members.
But moreover without caller silicon to speak of, Siena is still bringing immoderate hardware changes to nan AMD ecosystem. For nan motorboat of their lightweight server processor, AMD is introducing a caller server socket: Socket SP6. Taking advantage of nan little number of I/O lanes and representation channels utilized by Siena – not to mention nan smaller beingness footprint of nan reduced number of chiplets – socket SP6 chips are physically smaller and characteristic less LGA pads, designed to let for suitably cheaper motherboards.
|AMD Zen 4 CPU Sockets|
|AnandTech||Chip Dimensions (x/y)||Pin Count||PCIe 5.0 Lanes||Memory Channels||Max TDP
The LGA SP6 chips measurement 58.5 x 75.4 mm, down from 72 x 75.4mm for SP5, aliases are astir 81% of nan size. In position of pin counts, we’re looking astatine a still sizable 4844 pins, which is still down from nan 6096 pins utilized successful SP5. Overall, it does make for a spot of an overseas business to person nan only non-SP5 EPYC beryllium nan only EPYC without immoderate caller silicon successful it, but we fishy this will not beryllium nan only spot we spot SP6 complete nan coming years.
Altogether, AMD is rolling retired Siena pinch a sizable stack of 12 chips. There are fundamentally 6 tiers of chips, each differentiated by nan number of Zen 4c CPU cores available, pinch each tier disposable successful some a accepted spot aliases a fixed powerfulness Network Equipment-Building System (NEBS) friends configuration, which offers a wider somesthesia scope tolerance and is designed for deployments successful little controlled conditions.
|AMD EPYC 8004 Siena Processors|
|8534P||64||128||2300||3100||128MB||96 x 5.0||6 x DDR5-4800||200||155-255||$4,950|
The flagship Siena portion is nan EPYC 8534P, which offers 64 Zen 4c cores utilizing 4 Zen 4c CCDs. The default TDP connected this portion is 200 watts, pinch a cTDP scope of 115W up to 225W. For each applicable purposes this is half of an EPYC Bergamo 9754, offering half arsenic galore CPU cores, half arsenic overmuch L3 cache, half arsenic overmuch representation bandwidth, and depending connected really to dial successful nan cTDP, astir half nan TDP. Like nan Bergamo family, these chips are aimed astatine customers who request much CPU cores much than they request top-tier single-threaded performance, pinch nan Zen 4c CPU cores topping retired astatine conscionable 3.1GHz erstwhile boosting, and moving astatine a guidelines clockspeed of 2.3GHz. The 8534P’s NEBS counterpart, nan 8534PN, offers nan aforesaid spot configuration astatine a 175W fixed TDP, and a little guidelines clockspeed of 2.0GHz, each successful speech for a wider -5C to +85C operating range.
At nan different extremity of nan spectrum is nan EPYC 8024P. This portion features conscionable 8 CPU cores – AMD is utilizing a single, half-enabled Zen 4c CCD present – pinch nan L3 cache scaled down to that of a azygous CCD, each nan while nan afloat 6 channels of DDR5 representation and 96 PCIe lanes remain. This 8 halfway portion has a guidelines TDP of 90W, though that tin beryllium adjusted to beryllium betwixt 70W and 100W.
Otherwise, since AMD is utilizing nan aforesaid IOD arsenic their different EPYC parts, galore of nan limitations and trade-offs pinch those parts remain. The highest supported representation velocity is DDR5-4800, which tin only beryllium deed pinch 1 DPC. And not each of nan PCie lanes tin beryllium switched to CXL mode – successful this case, conscionable 48 lanes. Reflecting nan lower-cost quality of nan Siena platform, 3DS RDIMMs are not supported here, meaning that nan platform’s maximum representation capacity is 12x96GB (1.152TB) of DDR5 RDIMMs.
At first blush, I was amazed to spot that AMD kept nan aforesaid sizable EPYC IOD for their fund server part. But AMD has had astir a twelvemonth to stockpile defective IODs for salvage purposes. Arguably, a smaller IOD would beryllium superior from an power ratio standpoint, but that is counterbalanced by nan truth that AMD would request to walk nan clip taping retired a caller IOD for what is meant to beryllium a inexpensive portion that benefits from silicon reuse. I would beryllium a spot much amazed if AMD doesn’t do a smaller IOD for early generations of chips successful this merchandise segment, but arsenic has been nan lawsuit since nan commencement of AMD’s EPYC journey, they are taking things slow and steadily present arsenic they grow their server CPU offerings.
In immoderate case, pinch nan Siena/EPYC 8004 lineup, AMD is looking to thrust location nan costs statement for these chips, particularly compared to Intel’s 4th procreation Xeon (Sapphire Rapids) lineup. Since there’s nary caller silicon here, Siena doesn’t importantly alteration immoderate of nan calculus there, but Intel’s attraction connected accelerators versus AMD’s attraction connected all-out CPU capacity intends that AMD tin bring a batch of CPU cores to carnivore moreover successful cheaper configurations. Which, successful workloads that can’t return advantage of Intel’s accelerators, AMD believes gives them a important edge.
As always, vendor numbers should beryllium taken pinch a atom of salt. But AMD is reasonably assured successful nan expertise of their chips to clasp nan lead successful perf-per-watt, particularly erstwhile compared to a Xeon pinch a akin number of cores.
Wrapping things up, according to AMD, Siena chips are disposable now. The database prices scope from $5,450 down to $409 successful 1,000 portion quantities – while AMD’s bigger partners usually get amended deals than that. Speaking of which, galore of nan accustomed suspects successful nan server abstraction are launching caller platforms successful nan coming weeks based connected Siena, pinch Dell, Lenovo, and Supermicro each showing disconnected edge-optimized systems.